Continued miniaturization of silicon CMOS transistor technology has resulted in an unprecedented increase in single-core and multi-core performance of modern-day microprocessors. However, the exponentially rising transistor count has also increased the overall power consumption making performance per Watt of energy consumption, the key figure-of-merit for today's high-performance microprocessors. Today, energy efficiency serves as the central tenet of high performance microprocessor technology at the system architecture level as well as the transistor level ushering in the era of energy efficient nanoelectronics. Aggressive supply voltage scaling while maintaining transistor performance is a direct approach towards reducing the energy consumption since it reduces the dynamic power quadratically and the leakage power linearly. In MOSFETs, the OFF-state leakage current (IOFF) increases exponentially with reduction of threshold voltage. There are various leakage current mechanisms, such as band to band tunneling (BTBT) at the drain-channel junction, the gate tunneling leakage current through the ultra-thin gate dielectric and even direct tunneling from source to drain increases with continued scaling. Hence there is a fundamental limit to the scaling of the MOSFET threshold voltage and hence the supply voltage. Scaling supply voltage limits the ON current (ION) and the ION-IOFF ratio. This theoretical limit to threshold voltage scaling mainly arises from MOSFETs 60 mV/decade sub-threshold swing at room temperature and it significantly restricts low voltage operation.
Leakage power consumption in SRAMs has been a major concern in caches since the International Technology Roadmap for Semiconductors (ITRS) projected that the percentage of memory in System on Chip designs (SoCs) will increase from the current 84% to as high as 94% by the year 2014. As indicated above, low voltage operation is one of the most effective low power design techniques due to its quadratic dynamic and linear static energy savings. However, in current MOSFET-based designs, lower threshold voltages increase the sub-threshold current exponentially and ultra thin gate oxides cause a huge increase in gate current. Various methods such as multiple threshold voltages and increased gate oxide thicknesses have been explored to reduce leakage current in SRAMs. Adaptive or dynamic body biasing techniques have also been explored for this purpose.
Recently, leakage reduction using steep sub-threshold transistors has gained great attention. A steep sub-threshold transistor allows us to Operate at very low threshold voltages with ultra low leakage currents and low supply voltages (VDD). TFETs, which work on the principle of inter-band tunneling, have shown to be a promising steep sub-threshold transistor. However integration of TFETs into CMOS transistor technology is generally difficult, as the unidirectionality of TFET devices generally limits their applicability to memory devices or requires more complex memory cell architectures.